Thu, Sep 19, 2019

Currently in the second phase of India Chip Program the School of VLSI Technology has undertaken a Design of a Chip on Low Frequency, Low Jitter Clock Generator in collaboration with I.I.T, Kharagpur and the work is currently under progress.So far layout for the chip has been finalized.The post layout simulation and total Integration (which is to be done in IIT,Kharagpur along with other participating Institutes) is to be completed. The detailed specification for the chip is as follows:

DESIGN SPECIFICATION:

  • Power Supply 1.8V
  • Clock Frequency 256 KHz
  • Rise Time/Fall Time <0.1% of time period
  • Duty Cycle 50%
  • Jitter <80ns
  • Delay in inverted waveform < 1% of time period


Number of Ph Ds

Registered – 2

Enrolled -- Nil


Numbers of publications in 2009-2010

Accepted – 32

Submitted - 1