Thu, Sep 19, 2019

1. J.mathew,H.Rahaman and D.K.Pradhan,” Single Error Correcting Finite field multipliers over GF(2m)”,International Conference on VLSI Design 2008,India.

2. H.Rahaman,J.Mathew and D.K.Pradhan, “ A Galois based logic Synthesis Approach with testability”, International Conference on VLSI Design , 2008,India.

3. H.Rahaman,D.Kolay,D.K.Das and B.B.Bhattacharya, “Universal Test generation for different New fault models in Reversible Circuits”, International Conference on VLSIDesign 2008,India.

4. Nachiketa Das; Pranab Roy; Rahaman, H.,“On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element”, 14th IEEE International On-Line Testing Symposium,Rhodes,Greece,July,2008

5. Sudip Ghosh,Pranab Roy,Dr S.P.Maity,Dr H.Rahaman, “Spread Spectrum Image Watermarking with digital design”,IEEE International advanced computing conference,March 6 – 7,2009,patiala,India[Accepted and To be held]

6. N.Das,P.Roy,H.Rahaman,“Feedback Bridging Fault Detection in Cluster Based FPGA by Using Muller C Element”,ICFCC 2009 ,3 April,2009,Kulalampur,Malayasia [ Accepted]

7. Dr S Chakraborty,“Bridging fault detection of the reversible circuit”,Proceedings of the 3rd International design and test Workshop at Monastir,Tunisia,IEEE Computer Science press,2008

8. Dr S.Chakraborty,“Low Power Design by Circuit partitioning”,Proceedings of the International Conference on Computer,communication,control and information Technology,February,Kolkata,2009.