Sponsored Research / Fundings
Project V
Title: DEVELOPMENT OF AN EMERGENCY COMMUNICATION SYSTEM FOR VEHICLES USING INTERNET OF THINGS (IOT) FRAMEWORK.
Project Cost: 27.4 lacs + (INR) [excluding airfare and accommodation of the scholar]
Principal Investigator: Dr. Prasun Ghosal, IIEST, Shibpur, India and Dr. Saket Srivastava, University of Lincoln, UK
Research Scholar: Subha Koley [under Split-site PhD Fellowship]
Funding Agency: Commonwealth Scholarship Commission, UK
Duration: 1 year
Status: Ongoing.
Project IV
Title: PROGRAMMING AND DEVELOPMENT OF A SMART HOME AUTOMATION SYSTEM USING IOT FRAMEWORK
Project Cost: 30,000 (INR)
Principal Investigator: Dr. Prasun Ghosal
Student Members: Abhishek Tiwari, Simran Kaur (UG student)
Funding Agency: Institute of Engineers (India)
Date of Sanction: 11.05.2017 (vide order no. R.4/2/UG/2016-17/RDUG2016230)
Official date of commencement: 01.12.2017
Duration: 6 months
Project Overview:
Primary objective of the proposed project is to design an embedded system using IoT (Internet of Things) framework for smart home applications in tomorrow’s smart city perspective. Designed system will be capable of automatic monitoring as well as controlling different smart home objects. Raspberry Pi 3 will be used as the implementation framework.
Status: Ongoing.
Project III
Title: DEVELOPMENT OF OBSTACLE AWARE ROUTING TOOL FOR 3D INTEGRATED CIRCUITS
Project Cost: 50,000 (INR)
Principal Investigator: Dr. Prasun Ghosal
Student Members: Satrajit Das, Arindam Das (PG student)
Funding Agency: Institute of Engineers (India)
Date of Sanction: 13.07.2011 (vide order no. IEI/RDC/RD2011377)
Official date of commencement: 03.08.2011
Duration: 1 year
Project Overview:
Primary objective of the proposed project is to develop the obstacle aware routing algorithms during the physical design of 3D Integrated Circuits and thereby the development of the obstacle aware routing tool for 3D ICs.
Status: Successfully completed.
Project II
Title: DESIGN OF A LOW POWER, LOW SKEW, LOW JITTER, LOW FREQUENCY (256 KHz) CLOCK GENERATOR
Program: India Chip Design Program under SMDP - II (Special Manpower Development Project, Phase II)
Funding Agency: Ministry of IT, Govt. of India
Design style: Mixed signal, full custom
Technology used: UMC 180 nm
Design environment: Cadence
Project Overview:
Actively engaged in a collaborative VLSI chip design project under India Chip Design program of SMDP II (Special Manpower Development Project, Phase II) funded by Ministry of IT, Govt. of India in collaboration with IIT Kharagpur, Jadavpur University, NIT Durgapur, NIT Silchar, NIT Rourkella and NIT Jamshedpur. The complete design till layout of a low jitter, low skew, low frequency (256 KHz) clock generator is being carried out using Cadence and UMC 180 nm technology library.
Status: Successfully completed the design and implementation up to layout with successful post layout simulation verification. Final integration has been done. Chip is fabricated and tested. Test results are quite satisfactory. Here are the snapshots of the fabricated microchip.
Research Publications out of this project work: International Journal - 1, International Conference - 1.
Project I
Title: DEVELOPMENT OF LOW COST FPGA BASED EMBEDDED SYSTEMS FOR NETWORK ON CHIP APPLICATIONS
Project Cost: 6,50,000 (INR)
Principal Investigator: Dr. Prasun Ghosal
Co Principal Investigator: Dr. Hafizur Rahaman
Funding Agency: AICTE (All India Council for Technical Education)
Date of Commencement: April 11, 2008
Duration: 2 years
Project Overview:
Principal objective of this project work will be based on the development of the small embedded systems aimed to apply for the Network on Chip applications, a promising and challenging area in the Information Technology sector. Chip design has four distinct aspects: Computation, Memory, Communication, and I/O. As processing power has increased and data intensive applications have emerged, the challenges of the communication aspect in single-chip systems, Systems-on-Chip (SoC), has attracted increasing attention. Communication in SoC is known as Network-on-Chip (NoC). NoC does not constitute an explicit new alternative for intra-chip communication but is rather a concept that presents a unification of on-chip communication solutions. Hence, the main objective of this project thus will be to explore and design the networking solutions on SoC. Besides this to find the cost effective design solutions using FPGA (Field Programmable Gate Arrays) also.
Status: Successfully completed.
Research Publications out of this project work: International Journal: 2, International Conference: 2, Post-graduate thesis work: 2.