Publications

• S. Saha Ray, S. Singh, C. Sengupta, S. Ghosh and B. Sardar, “A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing”, 2018 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Indore, India, 16-19 December 2018.

• A. Sarkar and S. Ghosh, “A Coarse-Grained Pipeline Architecture for Sequence Alignment”, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18, 2018.

• D. Sharma, A. Gupta, A. K. Layek and S. Ghosh, “Movable Wireless Access Point for IoT-Based Home Automation”, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18, 2018.

• S. K. Ray and S. Ghosh, "Binarily Gapped Binary Insertion Sorting Technique", Institution of Electronics and Telecommunication Engineers (IETE) Journal of Research, Vol. 64, No. 3, 2018. pp 337-346, DOI: 10.1080/03772063.2017.1357506

• S. Ghosh and A. Sarkar, “An FPGA-Based Processor for Compact Sequence Alignment”, IEEE International conference on Electronics, Communication and Aerospace Technology (IEEE ICECA 2018), 2018.

• S. Ghosh, S. Kesharwani, V. Mishra and S. S. Ray, "Hybrid trie based approach for longest prefix matching in IP packet processing," TENCON 2017 - IEEE Region 10 Conference, 2017, Penang, pp. 1532-1537.

• S. S. Ray, N. Srivastava and S. Ghosh, “A Hardware-Based High-Throughput DNA Sequence Alignment Scheme”, India Conference (INDICON), 2016 Annual IEEE, Bengaluru, 2016. pp 1 -6, DOI: 10.1109/INDICON.2016.7838990

• S. S. Ray, S. Ghosh and B. Sardar, “SRAM Based Novel Hardware Architecture for Longest Prefix Matching for IP Route Lookup”, Photonic Network Communications – Springer, Vol. 32, No. 3, Dec. 2016, pp. 359 – 371, DOI: 10.1007/s11107-016-0674-8

• S. Saha Ray, A. Banerjee, A. Datta and S. Ghosh, “A Memory Efficient DNA Sequence Alignment Technique Using Pointing Matrix”, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016, pp. 3559 – 3562, DOI: 10.1109/TENCON.2016.7848720

• S. Ghosh and M. Baliyan, “A Hash Based Architecture of Longest Prefix Matching for Fast IP Processing”, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016, pp. 228 – 231, DOI: 10.1109/TENCON.2016.7847995

• S. Saha Ray, K. Das and S. Ghosh, “A RAM-Based MAC Table with Two-Tier Security at Layer 2”, IETE Journal of Research, (On line publication 7 Dec. 2015), Vol. 62, No. 4, pp. 435-445, 2016, DOI: 10.1080/03772063.2015.1117953

• S. S. Ray, S. Ghosh and B. Sardar, "SRAM based longest prefix matching approach for multigigabit IP processing," 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems (ANTS), Kolkata, 2015, pp. 1-6, DOI: 10.1109/ANTS.2015.7413624

• S. Ghosh, S. Mandal and S. Saha Ray, "A scalable high-throughput pipeline architecture for DNA sequence alignment," TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, 2015, pp. 1-6, DOI: 10.1109/TENCON.2015.7373055

• S. S. Ray, S. Ghosh, R. Prasad, “Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching,” India Conference (INDICON), 2014 Annual IEEE , pp.1-6, 11-13 Dec. Digital Object Identifier : 10.1109/INDICON.2014.7030681

• S. S. Ray, A. Bhattacharya, S. Ghosh, “A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification,” India Conference (INDICON), 2014 Annual IEEE , pp.1-6, 11-13 Dec. 2014. . Digital Object Identifier : 10.1109/INDICON.2014.7030357

• S. S. Ray, A. Chatterjee, S. Ghosh, “A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification,” TENCON 2014 - 2014 IEEE Region 10 Conference, pp.1-6, 22-25 Oct. 2014. Digital Object Identifier : 10.1109/TENCON.2014.7022466

• S. S. Ray, A. Chatterjee, S. Ghosh, "A Hierarchical High-throughput and Low Power Architecture for Longest Prefix Matching for Packet Forwarding", Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai, pp. 628-631, 26th-28th Dec. 2013. Print ISBN: 978-1-4799-1594-1, Digital Object Identifier : 10.1109/ICCIC.2013.6724271

• S. Ghosh, S. S. Ray, S. Mandal, "High Through-put Scalable Query Processing Architecture using STCAM", Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai, pp. 650-653, 26th-28th Dec. 2013, Print ISBN: 978-1-4799-1594-1, Digital Object Identifier : 10.1109/ICCIC.2013.6724274

• S. Saha Ray, S. Ghosh, “Smart Ternary Content Addressable Memory (STCAM) Architecture”, Ieee International Conference on Advanced Communication Control and Computing Technologies (Icaccct) (Available in IEEE Xplore Digital Library), Ramanathapuram, pp. 434 – 438, 23-25 Aug. 2012. Print ISBN: 978-1-4673-2045-0, DOI : 10.1109/ICACCCT.2012.6320817

• S. Ghosh, J. Ghosh, S. Saha Ray, “Architecture of Configurable K-way C-access Interleaved Memory”, International Conference on Process Automation Control and Computing (ICPACC) (Available in IEEE Xplore Digital Library), Coimbatore, 20-22 July 2011. Print ISBN: 978-1-61284-765-8, DOI: 10.1109/PACC.2011.5978873

• S. K. Ray, S. Ghosh, “Low-Cost dictionary machine using RAM -Based CAM”, International Conference on Advanced Computing (ICAC 09), Tiruchirappalli, Aug. 6-8, pp. 559-566, 2009

• S. Ghosh, S. Saha Ray, “Register Size Programmable Autoconfigured Register Size for RISC Processors”, Proceedings of International Conference on Embedded Systems and VLSI Design (ICVLSI), Chennai, Feb 14-16, 2008

• S. Ghosh, S. Saha Ray, “4th Generation Progrqammable Logic Computing: A Road Map”, IETE Technical Review, Volume 24, No. 6, pp. 439 - 452, 2007